Program:

 module jk_ff

(input j,k,clk,output reg q); 

wire q_bar;

not(q_bar,q);

 always@(posedge clk)

begin

if(!j)

begin

if(!k)

q = q;

else

q = 0;

end

 else

begin

if(!k)

q = 1;

else

q = q_bar;

end

 end

 endmodule