To implement synchronous and asynchronous counters using Verilog HDL.(RING & JOHNSON)

 

Program of 4 Bit synchronous ring Counter using Behavior Model:

 module Counter_4Bit ( clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input clk ;

wire clk ;

input reset ;

wire reset ;

initial dout = 0;

always @ (posedge (clk)) beginif (reset) dout <= 0;

else

dout <= dout + 1;

end

endmodule

 

Program of 4 Bit Asynchronous ring Counter using Behavior Model:

module counter( clk, count );

input clk;

output[3:0] count;

reg[3:0] count;

wire clk;

initial

count = 4'b0;

always @( negedge clk ) count[0] <= ~count[0];

always @( negedge count[0] ) count[1] <= ~count[1];

always @( negedge count[1] ) count[2] <= ~count[2];

always @( negedge count[2] ) count[3] <= ~count[3];

endmodule