Program

module sr_ff

(input s,r,clk,output reg q);

 wire q_bar;

 not(q_bar,q);

 always@(posedge clk)

begin

if(!s)

begin

if(!r)

q = q;

else

q = 0;

end

else

begin

if(!r)

q = 1;

else

q = 1'bx;

end

end

 endmodule