To Design and verify a model for 32 bit ALU using verilog HDL

Program of 32-bit ALU:

module alu( a, b,cout,opcode,zout );

input [31:0] a,b;

outputcout;

input[2:0] opcode;

output [31:0]zout;

reg [32:0]temp;

always@(*)

begin

case(opcode)

       3'b000: temp = a + b;

       3'b001: temp = a - b;

       3'b010: temp[31:0]= ~a;

       3'b011: temp= a[15:0]* b[15:0];

       3'b100: temp[31:0]= a & b;

       3'b101: temp[31:0]= a | b;

       3'b110: temp[31:0]= ~(a & b);

       3'b111: temp[31:0]= a ^ b;

      default : temp= 32'd0;

endcase

end

assignzout=temp[31:0];

assigncout=temp[32];

endmodule