To design and verify the truth table of a 4:1 multiplexer and 1:4 demultiplexer using Xilinx software.

Multiplexer

module multiplexer4_1 ( I0 ,I1 ,I2 ,I3 ,S1 ,S2 ,Y );

output Y ;

input I0 ;

input I1 ;

input I2 ;

input I3 ;

input S1 ;

input S2;

assign Y = (I0 & (~S1) & (~S2)) | (I1 & (~S1) & (S2)) | (I2 & S1 & (~S2)) |(I3 & S1 & S2);

endmodule

 

Demultiplexer

module demultiplexer1_4 ( Din ,S1 ,S2 ,Y0 ,Y1 ,Y2 ,Y3 );

output Y0 ;

output Y1 ;

output Y2 ;

output Y3 ;

input Din ;

input S1 ;

input S2 ;

assign Y0 = Din & (~S1) & (~S2);

assign Y1 = Din & (~S1) & S2;

assign Y2 = Din & S1 & (~S2);

assign Y3 = Din & S1 & S2;

endmodule