To implement half-adder and full-adder combinational circuits using Verilog HDL.

Program of Half Adder:
Gate Level Modelling:
Module halfadder(a, b, sum, carry);
inputa,b;
output sum, carry;
xor (sum,a,b);
and (carry, a,b);
endmodule

Dataflow Modelling:
Module halfadder(a,b,sum,carry);
input a; input b; output sum;
output carry ; 
assign sum=a ^ b ;
assign carry=a & b;
endmodule

Behavioral Modelling:
 
module halfadder (a,b,sum,carry);
input a; input b; 
output sum; output carry ;
reg sum, carry; 
always@(a,b) begin sum=a^b; 
carry=a&b; 
end
endmodule
 
Program of Full Adder:
Gate Level Modelling:
Module fulladder (a, b, c, sum, carry); 
input a,b,c;
output sum,carry; 
wire x,y,z;
xor n1(x,a,b);
and n2(y,a,b);
xor n3(sum,x,c);
and n4(z,a,c);
or n5(carry,y,z); 
endmodule

Dataflow Modelling:
Module fulladder (a, b, c, sum, carry); 
input a,b,c;
output sum,carry; 
wire x,y,z; 
assign x=a^b; 
assign sum=x^c; 
assign y=a&b; 
assign z=x&c; 
assign carry=z|y;
endmodule
 
Behavioral Modelling:
module fulladder (a, b, c, sum, carry); 
input a,b,c;
output sum,carry; reg sum,carry; regx,y,z; 
always@(a,b,c) begin
x=a^b; 
sum=x^c; 
y=a&b;
z=x&c; 
carry=z|y;
end
endmodule