To implement a decoder and encoder combinational circuits using Verilog HDL

Program of 4 to 2 Encoder:

 moduleencoder4_2 ( a ,b,c,d,x,y);

output x ;

output y ;

input a ;

input b ;

input c ;

input d ;

assign x = b | d;

assign y = c | d;

endmodule

Program of 2 to 4 Decoder:

 moduledecoder2_4 ( a ,b ,w,x ,y ,z );

output w ;

output x ;

output y ;

output z ;

input a ;

input b ;

assign w = (~a) & (~b);

assign x = (~a) & b;

assign y = a & (~b);

assign z = a & b; endmodule