Showing posts with the label DIGITAL ELECTRONICS LABORATORY MANUALShow all
To implement synchronous and asynchronous counters using Verilog HDL.(RING & JOHNSON)
Program of 4 Bit synchronous ring Counter using Behavior Model: module Counter_4Bit ( clk ,re…
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To develop T flipflop using Verilog HDL
Program: module t_ff (input t,clk,output reg q); wire q_bar; not(q_bar,q); initial begin q = 1…
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To develop JK flipflop using Verilog HDL
Program: module jk_ff ( input j,k,clk, output reg q ); wire q_bar; not(q_bar,q); always@(po…
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To develop D flipflop using Verilog HDL
Program: module d_ff (input d,clk, output reg q ); wire q_bar ; not(q_bar,q) ; always@(posedg…
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To develop SR flipflop using Verilog HDL
Program module sr_ff ( input s,r,clk, output reg q ); wire q_bar; not(q_bar,q); always@(posed…
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